Introduction to the special issue on Radio Frequency Integrated Circuits (RFIC) design techniques

Peer reviewe

Pixel design and evaluation in CMOS image sensor technology

A chip designed in a 0.18 μm CMOS Image Sensor Technology (CIS) is presented which incorporates different pixel design alternatives for Active Pixel Sensor (APS). CIS technology improves characteristics such as sensitivity, dark current and noise, that are strongly layout dependent. This chip includes a set of pixel architectures where different parameters have been modified: layout of active diffusion, threshold voltage of the source follower transistor and the use of microlenses. Besides, structures to study the influence of crosstalk between pixels have been incorporated

Macromodelling for analog design and robustness boosting in bio-inspired computing models

Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100×150 pixels. Moreover, introducing an optical input in the low level simulation is nowadays not feasible with standard electrical simulation environments. Given that, to accomplish the task of integrating those systems in silicon to build compact, low power consuming, and reliable systems, a previous step in the standard analog electronic design flux should be introduced. Here a methodology to make the translation from the biological model to circuit-level specifications for electronic design is proposed. The purpose is to include non ideal effects as mismatching, noise, leakages, supply degradation, feedthrough, and temperature of operation in a high level description of the implementation, in order to accomplish behavioural simulations that require less computational effort and resources. A particular case study is presented, the analog electronic implementation of the locust's Lobula Giant Movement Detector (LGMD), a neural structure that fires a collision alarm based on visual information. The final goal is a collision threat detection vision system on-chip for automotive applications.European Union IST-2001-38097, TIC2003 - 09817-C02-0

Load-independent characterization of trade-off fronts for operational amplifiers

Abstract—In emerging design methodologies for analog integrated circuits, the use of performance trade-off fronts, also known as Pareto fronts, is a keystone to overcome the limitations of the traditional top-down methodologies. However, most techniques reported so far to generate the front neglect the effect of the surrounding circuitry (such as the output load impedance) on the Pareto-front, thereby making it only valid for the context where the front was generated. This strongly limits its use in hierarchical analog synthesis because of the heavy dependence of key performances on the surrounding circuitry, but, more importantly, because this circuitry remains unknown until the synthesis process. We will address this problem by proposing a new technique to generate the trade-off fronts that is independent of the load that the circuit has to drive. This idea is exploited for a commonly used circuit, the operational amplifier, and experimental results show that this is a promising approach to solve the issue

Mixed-mode impedance and reflection coefficient of two-port devices

From the point of view of mixed-mode scattering parameters, Smm, a two-port device can be excited using different driving conditions. Each condition leads to a particular set of input reflection and input impedance coefficient definitions that should be carefully applied depending on the type of excitation and symmetry of the two-port device. Therefore, the aim of this paper is to explain the general analytic procedure for the evaluation of such reflection and impedance coefficients in terms of mixed-mode scattering parameters. Moreover, the driving of a two-port device as a one-port device is explained as a particular case of a two-port mixed-mode excitation using a given set of mixed-mode loads. The theory is applied to the evaluation of the quality factor, Q, of symmetrical and non- symmetrical inductors.Ministerio de Innovación y Ciencia TEC2010-14825/MIC, TEC2010-21484Junta de Andalucía TIC-253

Tactile on-chip pre-processing with techniques from artificial retinas

The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in tele-presence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide can be managed with many image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look to the skin, the information collected by every mechanoreceptor is not carried to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. This is also the behavior of the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results when it faces the detection of the slip, which involves fast real-time processing.Ministerio de Ciencia y Tecnología TIC2003 - 09817-C0

A multimode gray-scale CMOS optical sensor for visual computers

This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural net) chips. The sensor offers to the user the possibility of choosing the photo-sensitive device as well as the mechanism for transducing the photogenerated charges into the correspondent pixel voltage. Both linear or logarithmic compression acquisition modes are available. This makes the sensor very suitable to be used in very different illumination conditions.Office of Naval Research (USA) N0014-WC-0295Comisión Interministerial de Ciencia y Tecnología TIC 1999-082

A versatile sensor interface for programmable vision systems-on-chip

This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35μm n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 × 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 × 12.230mm2 and cell size is 75.7μm × 73.3μm. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.European Commission IST-1999-19007Office of Naval Research (USA) N00014021088

Mixed-signal CNN array chips for image processing

Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions